Electronic devices such as mobile phones, tablet terminals, note-type personal computers (PCs), desktop PCs, game devices, etc. may include a processor for performing operation processing such as a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller, etc.
As semiconductor manufacturing processes become sophisticated, the number of peripheral circuits increases, and a demand for low power consumption continues to grow, an electronic device equipped with a processor is finely divided into tens of circuit blocks, and the supply voltage applied to each of the circuit blocks is individually controlled.
Such a device may employ a power management integrated circuit (PMIC) in order to control tens of power supply systems associated with tens of circuit blocks. The PMIC is required to accurately control tens of power sources by turning them on/off in a predetermined sequence.
FIG. 1 is a block diagram of an electronic device 1r. The electronic device 1r includes a PMIC 70, a CPU 20, a battery 30, a charging circuit 40, peripheral circuits 50, and a power-on key 60.
The battery 30 may be a lithium-ion battery, a nickel-hydrogen battery, etc., and outputs a battery voltage VBAT. An external DC power source 2 such as an AC adaptor, a USB host, etc. is detachably connected to an external terminal EXT of the electronic device 1r, into which a DC voltage VDC is supplied. The charging circuit 40 receives a DC voltage VDC from the DC power source 2 to charge the battery 30. Further, the charging circuit 40 selects one from the battery voltage VBAT and the DC voltage VDC, and outputs a system voltage VSYS via a system terminal SYS.
The PMIC 70 receives the system voltage VSYS. In one embodiment, the PMIC 70 receives the system voltage VSYS at its power input terminal. The PMIC 70 includes a plurality of power circuits that generates supply voltages VDD1, VDD2, . . . , VDDN with regulated voltage levels, a power management controller that controls a start sequence and timing of the plurality of power circuits, and an oscillator 702. The plurality of power circuits 22 may include a step-up DC/DC converter, a step-down DC/DC converter, a step-up/step-down DC/DC converter, a charge pump circuit, a linear regulator such as a low drop output (LDO) regulator, etc. The power management controller of the PMIC 70 initiates turning on of the plurality of power circuits when a power-on signal PWRON from the CPU 20 is asserted. The starting timing and the operating time period are managed based on clock signals CLK generated by the oscillator 702.
For example, the supply voltages VDD1 to VDD3 are supplied to the CPU 20. Each of the supply voltages VDD4 and VDD5 is supplied to the peripheral circuits 50. The peripheral circuits 50 may include a random access memory (RAM), a hard disk drive, etc.
The power-on key 60 is a main power switch of the electronic device 1r. For example, when a user presses down the power-on key 60, the electronic device 1r is powered on/off. In order to prevent a malfunction of the power-on key 60, the electronic device 1r is powered on/off if the power-on key 60 is pressed and held for a predetermined time period.
A real time clock (RTC) 202 is disposed in the CPU 20. The CPU 20 determines whether the power-on key 60 has been pressed and held for a predetermined time period using clock signals (also referred to as calendar clocks) generated by the RTC 202. If so, the CPU 20 asserts the power-on signal PWRON for the PMIC 10. Once the power-on signal PWRON is asserted, the PMIC 10 initiates generating the supply voltages VDD1 to VDD5.
In the electronic device 1r of FIG. 1, the CPU 20 is required to determine whether the power-on key 60 has been turn on or off before the supply voltages VDD1 to VDD3 are applied thereto. To this end, the CPU 20 has a terminal at which the system voltage VSYS is directly applied. One of the circuit blocks of the CPU 20 that determines whether the power-on key 60 has been pressed is applied with the system voltage VSYS.
Some circuit blocks of the CPU 20 that receive the supply voltages VDD1 to VDD3 may be completely shut down while the supply voltage VDD is terminated, and thus, these circuit blocks of the CPU 20 consume almost zero power. On the other hand, one circuit block of the CPU 20 that determines whether the power-on key 60 has been pressed is required to be operating all the time. Accordingly, the CPU 20 of the electronic device 1r cannot entirely be shut down and thus consuming power.
In addition, as the system voltage VSYS is selected from the battery voltage VBAT or the DC voltage VDC, e.g., between 3 V to 5 V, it is higher than other supply voltages VDD1 VDD3 applied to the CPU 20, e.g., 1.5 V, 1.8 V and 3.5 V. Accordingly, a circuit block of the CPU 20 that generates the power-on signal PWRON is operated with the system voltage VSYS although it can be operated with a lower power voltage, e.g., 1.5 V. As a result, more power than necessary is consumed.